1. Field of the Invention
The invention relates to a printed circuit board (PCB), and more particularly, to bonding pad(s) for a printed circuit board for a semiconductor package and a method for forming bonding pad(s).
2. Background of the Related Art
In general, as multi-functional electronic devices increase in capacity and become more compact in size, semiconductor packets mounted in the electronic devices must become smaller. Accordingly, a semiconductor package in a ball grid array (BGA) form has been developed which is utilized by attaching solder balls at an upper surface of the printed circuit board of the semiconductor package, in place of outer leads emanating from a semiconductor package. This type of conventional semiconductor package will now be described with reference to FIG. 1.
FIG. 1 is a schematic plan view of a printed circuit board used for fabrication of a semiconductor package in a BGA form in accordance with a conventional art. As shown in FIG. 1, an assembly of a printed circuit board (PCB) 1 includes a cavity 2 formed at the center of the PCB 1 to accommodate a semiconductor chip (not shown) thereon, bonding pads 3 formed at an outer side of the cavity 2 and connected to the semiconductor chip by, for example, gold wire (not shown), and a plurality of external terminal lands (that is, ball bump lands in this case) 4 formed at an exterior of the bonding pads 3 and connected to a circuit pattern (not shown) formed inside the PCB 1.
In assembling the semiconductor package, the semiconductor chip is inserted and attached into the cavity 2 formed at the center of the PCB 1. The attached semiconductor chip and the bonding pads 3 are connected by the gold wire (not shown), whereby the semiconductor chip and the PCB 1 are electrically connected. Thereafter, in order to protect the semiconductor chip, the semiconductor chip and the wire are molded using an epoxy compound.
The bonding pads 3 will now be described with reference to FIG. 2.
FIG. 2 is an enlarged schematic view of bonding pads in accordance with the conventional art. As shown in FIG. 2, the bonding pads 3 are exposed externally, and a photo solder resist (PSR) 6 is applied on the circuit patterns 5 connected to the bonding pads 3. The PSR 6 is applied to protect the circuit pattern 5.
The bonding pads 3 will now be described in detail with reference to FIG. 3.
FIG. 3 is a schematic sectional view taken along line A-A′ of FIG. 2. As shown in FIG. 3, the bonding pad 3 includes an insulation layer 7 applied at an upper surface of the PCB 1, a copper pattern 8 formed at an upper surface of the insulation layer 7, and a nickel plating layer 9 and a gold plating layer 10 sequentially formed on the upper surface of the copper pattern 8.
The copper pattern 8 is formed by removing an unnecessary portion of copper clad laminate (CCL). The CCL is formed by attaching copper foil at one or both sides of the PCB 1 with the insulation layer 7 formed therein and using a general etching process, which will now be described in detail.
First, the copper foil is attached at an upper surface of the insulation layer 7 by using an adhesive 12. In order to increase the strength of the adhesive, the surface of the insulation layer 7 is made rough. A concave-convex portion 11 is formed at a lower surface of the copper foil. In order to increase attachment strength, a chromium (Cr) film 13 is applied on the surface of the concave-convex portion 11. The copper foil is then attached on the upper surface of the insulation layer 7 using the adhesive 12.
Thereafter, the nickel plating layer 9 and the gold plating layer 10 are sequentially formed on the upper surface of the copper pattern 8, thereby completing the bonding pad 3.
However, in removing the copper foil using the etching process to form the bonding pad 3 according to the conventional art, the chrome component remains at the left and right lower portions of the copper pattern 8. That is, the remaining chrome component protrudes from the left and right lower portions of the copper pattern 8. When the nickel plating layer 9 and the gold plating layer 10 are sequentially formed on the copper pattern 8, the nickel plating layer 9 and the gold plating layer 10 are formed so that they cover the outer side of the copper pattern 8 on the upper surface and at both side faces of the copper pattern 8.
However, the nickel plating layer 9 and the gold plating layer 10 are also sequentially formed on the surface of the chromium, which protrudes at the base of the bonding pad 3 as indicated by ‘L’ in FIG. 3.
Thus, since the nickel plating layer 9 and the gold plating layer 10 are formed protruded at both the left and right lower portions of the copper pattern 8, the space between adjacent bonding pads 3 becomes narrow, so that there is a limitation to accomplishing a fine pitch of the bonding pad 3.
For example, since the plating layers 9 and 10 are not formed protruded at the upper left and right portion of the copper pattern 8, the pitch interval between the adjacent wire bonding pads can be reduced. But when it comes to the lower portion of the copper pattern 8, since the distance between the left and right lower portions of the adjacent copper patterns 8 is narrower than the distance between the left and right upper portions of the copper patterns 8, it is not possible to reduce the interval between adjacent bonding pads.
As described above, the bonding pad of the PCB for a semiconductor package in accordance with the conventional art has the problem that, as the nickel plating layer 9 and the gold plating layer 10 are formed on the surface of the remaining chrome that protrudes from the left and right lower sides of the copper pattern 8 formed inside the bonding pad, it is not possible to reduce the interval between adjacent bonding pads.